Lenovo X220 (Maximized)
Table of contents
⚠️ EOL: No microcode updates
This board’s CPU generation has reached End of Servicing Updates. See per-board EOL/ESU status for ESU dates and Heads threat model for security implications.
✅ PROTECTED: TPM GPIO Reset
Pre-Skylake — dedicated PLTRST# pin. See Per-Board Protection Status, TPM GPIO Reset Vulnerability.
USB3: no integrated xHCI; the single X220 board covers both the i5 and i7 SKUs, and the i7 SKU’s discrete Renesas/NEC controller means Heads keeps USB3/xHCI enabled — see Install an OS → USB3.
Hardware Compatibility
Hardware: x220 — see the Hardware Compatibility List.
⚡ Safety First
Before starting, please read our SPI Programmer Best Practices guide for essential safety information and programmer recommendations.
Disassembly
The X220 has a single 8 MB SPI flash chip located under the palm rest. Disassembly requires keyboard and palm rest removal — similar to the X230. Full disassembly to access the SPI chip is documented in coreboot:
→ coreboot Sandy Bridge series (8MB SPI, in-circuit=yes, socketed=no)
→ coreboot X2xx series disassembly (keyboard + palmrest removal)
→ coreboot T420 (similar Sandy Bridge disassembly)
→ Libreboot X220 external flashing guide (disassembly photos, flashing commands)
→ X220 Hardware Maintenance Manual
Critical: Remove all batteries (including CMOS) AND disconnect the AC adapter before starting.
Flashing
The X220 uses a single 8 MB SPI flash chip – no ROM splitting needed. Follow the X230 flashing guide for flashing commands, substituting the X220 board name. Use [flasher] of your choice (flashrom or flashprog – see Tool Interchangeability) with the programmer you selected ([programmer] – see Programmer Selection):
sudo [flasher] --programmer [programmer] --chip YYY --write ~/heads/build/x86/x220-maximized/x220-maximized.rom
See the SPI Programmer Best Practices for programmer recommendations.